The present invention relates to a surface processing method of a specimen and an apparatus for processing the specimen, and in particular, it relates to a surface processing method and its apparatus suitable for plasma-etching the surface of a specimen on which semiconductor elements and the like are to be formed.
The prior art will be explained below using an apparatus for etching semiconductor elements, for example, an apparatus called an ECR (Electron Cyclotron Resonance) system. This system generates a plasma by exciting an inert gas in a vacuum container to which a magnetic field is applied from the outside. The magnetic field causes electrons to move in a cyclotronic motion. The cyclotron frequency and the microwave frequency in resonance generate a plasma efficiently. To accelerate plasma particles (ions) and make them go fast enough before striking a target in their path, a high-frequency voltage is applied to the target. A halogen gas such as chlorine gas or fluorine gas is used for generation of a plasma gas.
A high-precision type surface treating apparatus is disclosed in Japanese Non-examined Patent Publication No. 06-151360 (1994). This patent publication discloses that the intermittent on/off control of a high-frequency voltage applied to the target increases the selectivity of a surface substance (silicone) to be etched from the ground (oxide film) of a target and makes the etching rate less independent of conductor patterns. Further, in Japanese Non-examined Patent Publication No. 62-154734 (1987), there is disclosed a method of intermittently turning on and off high-frequency voltage and etching the slanted areas with a high-depositing etching gas. Furthermore, in Japanese Non-examined Patent Publication No. 60-50923 (1985), there is disclosed a method of intermittently turning on and off a high-frequency voltage according to the supply quantity of an etching gas to increase the anisotropy. Furthermore, U.S. Pat. No. 4,585,516 discloses a 3-electrode etching apparatus and a method of intermittently turning on and off a high-frequency voltage across two of such electrodes to assure a uniform etching speed over the whole wafer.
Along with a recent trend for finer patterning of semiconductor elements, a problem of damages of semiconductor devices caused by the plasma used in the processing thereof is becoming substantial and drawing more attention. More specifically, a typical thickness of a gate oxide film of metal oxide semiconductor (MOS) is less than 6 nm in the memory devices after the introduction of 256 M. In addition to the demand for a thinner film of such gate oxide film, when an aspect ratio (a ratio of vertical to lateral directions) in the processing becomes greater, an electrical damage caused by a so-called electron shading phenomenon becomes substantial. With reference to accompanying drawings:, this electron-shading phenomenon will be described in the. following. FIG. 24(1) shows a cross-sectional view of a semiconductor wafer exposed to plasma within an etching apparatus. FIG. 24(2) is a plan view of a resist pattern of FIG. 24(1) observed from the above. A device insulation oxide film 204 and a gate oxide film 203 are formed on a Si substrate 205, then on these films a poly-Si layer 202 and a resist 201 are formed in a comb pattern. During plasma etching, electrons 206 and ions 207 are bombarded on the specimen. Ions 207, which are accelerated by a high frequency voltage applied to the specimen, impinge on the surface of the specimen directly in the vertical direction. Electrons 206, which have a small mass and therefore have random speed components impinge on the specimen in random directions. Therefore, for processing of the surface with a groove having a high aspect ratio as shown in FIG. 24(1), although ions can reach the bottom of the groove 208, most of electrons are captured by side walls of resist 201. Then, positive charges are accumulated in gate oxide film 203 via poly-Si layer 202, and when an amount of this charge exceeds a predetermined value, the gate oxide film 203 is caused to breakdown, thereby resulting in a device failure. This phenomenon described above that prevents electrons from being supplied to the bottom of a fine patterned groove due to a difference in the directivities of ions and electrons is called electron shading.
Further, as smaller semiconductor elements have been required, finer patterning and working of them is essential. For example, recent semiconductor circuit patterns have lines and spaces (which are equivalent to wires and electrodes on semiconductor elements) of 0.3 microns or narrower. However, the conventional etching processes cannot satisfy such a fine patterning requirement. Necessarily, the etched lines are wider than required and resulting patterns are undesirable. Further, the etching status is greatly affected by a difference between the speed of fine-line etching and the speed of wide-space etching and a difference in shapes (shape micro loading). Furthermore, as the oxide film of a gate of a MOS (Metal Oxide Semiconductor) transistor (for memory chips of 256 MB or higher) is very thin (6 nm or less), its etching status is greatly affected by the anisotropy and the ratio of ground selectivity (ratio of selecting an oxide film as the ground) which are inverse-proportional to each other.
Therefore, an object of the invention is to provide for a surface processing method and an apparatus thereby, which can substantially reduce the damage of the semiconductor device due to this electron shading.
The other object of the present invention is to provide a surface treating method and apparatus which can increase the anisotropy and the ratio of ground selectivity in fine pattern etching processes.
Above one object of the invention can be accomplished by provision of a fine pattern etching processing method which is performed by applying a high frequency voltage to the specimen, and which is comprised of the steps of repeating: turning off the high frequency voltage applied to the specimen before a charged voltage of the pattern reaches an insulation breakdown voltage of the gate oxide film to which the pattern is connected; and turning on the high frequency voltage when the charged voltage of the pattern becomes sufficiently low.
The other object of the invention can be accomplished a process of fine pattern etching by a surface treating apparatus comprising a vacuum chamber, a means for generating a plasma in said chamber, and a high-frequency power supply which applies a high-frequency voltage across a target wafer and a target table which holds a target wafer to be etched by the plasma; wherein the amplitude of the high-frequency voltage is increased to improve the wall-to-bottom perpendicularity in etching and the high-frequency power supply is so controlled to turn on and off intermittently.